Generally, a System On Chip (SOC) is manufactured by integrating a set of system components onto a single chip. These system components may communicate with each other by utilizing available interconnects and buses. The interfaces between the system components would typically be externally visible (i.e., outside the SOC) if the system components were packaged individually. However, as these interfaces are not coupled externally in an SOC, the visibility of the interfaces is lost at the SOC level.
One solution is to provide dedicated pins on the SOC package to enable observability of these interfaces to the external world, e.g., for post-silicon debug. Considering the differential nature of these interfaces, sometimes 50-100 dedicated pins are needed on the package to obtain complete visibility. Another option is to provide bumps on the top of the package to enable interconnection with the internal link(s) via probes. The former solution, however, may increase the complexity of routing of interconnection pins, while the latter solution may mandate the need for additional layers of the die. Either option increases the amount of connections and package real estate, and thus raises costs.